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v0.22

a2792589 · Utopia EDA v0.22. · Oct 07, 2025
v0.21

adebd2be · Removed StatAggregator. · Oct 02, 2025
v0.20

d1fbc7e5 · write_aiger_bug_fix (A. Kurganskaya) · Sep 30, 2025
v0.19

05ab75c5 · connect all outputs with assign in verilog printer (N. Chertpl) · Sep 25, 2025
v0.18

fceba200 · Merge branch 'angband-main' (S. Smolov) · Sep 23, 2025
v0.17

af3784a9 · Merge remote-tracking branch 'origin/update_get_stat' into main · Sep 23, 2025
v0.16

845eebba · Merge branch 'add_library_diagnostics' (I. Chernyavskih) · Sep 19, 2025
v0.15

5a7f5cd8 · Add hard cells reading to library to support memory cells (E. Belin) · Sep 19, 2025
v0.14

7c5fa7c8 · BDD returns empty counterexmaple if no inputs (D. Usachev). · Sep 12, 2025
v0.13

e14e7ca4 · Bugfix/seq rst val (N. Chertok) · Sep 11, 2025
v0.12

7015fb6c · support soft macro blocks in Design (N. Chertok) · Sep 11, 2025
v0.11

d5bd1976 · Fixed warnings in Design. · Sep 11, 2025
v0.10

bdb291fb · Get techmap statistics (A. Kurganskaya). · Sep 03, 2025
v0.9

d0646289 · Removed {write,read}_snapshot commands. · Sep 02, 2025
v0.8

4036aae5 · Frontend, RTLIL, Yosys: removed generic Yosys frontend (M. Litvinov). · Aug 29, 2025
v0.7

8845fde9 · Fixed conflicts. · Aug 26, 2025
v0.6

4ad2be10 · SubnetBuilder refactoring (to be continued). · Aug 13, 2025
v0.5

9b1348d3 · Merge branch 'main' of https://gitlab.ispras.ru/mvg/utopia-eda into main · Aug 11, 2025
v0.4

10ebc1d5 · DefaultMapping contains pinIds with same direction (D. Usachev). · Aug 06, 2025
v0.3

b82f809a · lec_subnet_main.cpp: add rearrangeEntries (D. Usachev) · Jul 24, 2025

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