Merge requests · mvg / Utopia EDA · GitLab

Added maybe-unused in DesignEstimator

!870 · created Aug 01, 2025 by Камкин Александр Сергеевич
- Merged
updated Aug 01, 2025
added paths in LecGoal

!869 · created Aug 01, 2025 by Усачев Даниил Сергеевич
updated Aug 05, 2025
Preliminary implementation of read_snapshot

!868 · created Aug 01, 2025 by Камкин Александр Сергеевич
- Merged
updated Aug 01, 2025
add CommonGenTest

!867 · created Aug 01, 2025 by Черток Никита Дмитриевич
updated Aug 01, 2025
Downgrade required cmake version from 3.28 to 3.25

!866 · created Jul 31, 2025 by Лупанов Арсений Дмитриевич
updated Aug 05, 2025
Seq elem

!865 · created Jul 31, 2025 by Черток Никита Дмитриевич
updated Jul 31, 2025
Added the preliminary implementation of write_snapshot

!864 · created Jul 31, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 31, 2025
DefaultMapping hardBlock test

!863 · created Jul 31, 2025 by Усачев Даниил Сергеевич
updated Aug 04, 2025
Function for a design mapping writing in json.

!862 · created Jul 31, 2025 by Вершков Максим Дмитриевич
updated Jul 31, 2025
read_(system)verilog: --log option.

!861 · created Jul 31, 2025 by Литвинов Михаил Юрьевич
updated Aug 01, 2025
Separated ContextDesign from UtopiaContext

!860 · created Jul 31, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 31, 2025
Printing attributes before module name (not instance)

!859 · created Jul 31, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 31, 2025
Draft: debug percy test

!858 · created Jul 30, 2025 by Черток Никита Дмитриевич
- Closed
updated Jul 31, 2025
Added ability to read design to particular point

!857 · created Jul 30, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 30, 2025
Empty basis type was added.

!856 · created Jul 29, 2025 by Вершков Максим Дмитриевич
updated Jul 30, 2025
Saving cell attributes on Design-to-Net transform

!855 · created Jul 29, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 29, 2025
Random subnet techmap, print & read Verilog

!854 · created Jul 29, 2025 by Штренев Владислав
updated Aug 01, 2025
NetPrinterAiger: Incapsulating the aiger library in cpp

!853 · created Jul 29, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 29, 2025
Added debug-info attributes printing in Verilog

!852 · created Jul 29, 2025 by Камкин Александр Сергеевич
- Merged
updated Jul 29, 2025
DesignSimulator v2

!851 · created Jul 28, 2025 by Ершов Михаил Алексеевич
Model Simulator
updated Aug 11, 2025

Prev
1
2
3
4
5
6
7
8
9
10
…
48
Next