Import design metadata from RTLIL
Metadata required:
- source location for cells a.k.a. debug info
- hierarchical names
Source location is imported as is for every cell with the attribute.
Hierarchical names are derived as follows:
- if a cell has a public name, it is used as is (module instances, including library cells and macro blocks);
- if a cell with internal name has a single output (wire) with public name, the name of the wire is used (w.r.t. slices, e.g
in[1:0]
orin[0]
); - otherwise cell name is not set.