verilog_openabcd/rw/mix_oabcd.v
The commit includes mix_oabcd.v Verilog description that is synthesized
from the initial one using Utopia EDA logic synthesis tool with 'logopt rw' pass.
Signed-off-by: Sergey Smolov smolov@ispras.ru
The commit includes mix_oabcd.v Verilog description that is synthesized
from the initial one using Utopia EDA logic synthesis tool with 'logopt rw' pass.
Signed-off-by: Sergey Smolov smolov@ispras.ru