Original design assumes bigger port widths in connections to module 'ramb4_s4_s4'. (!3) · Merge requests · mvg / mvg-rtl / benchmark / hdl-benchmarks

This results in the use of uninitialized values which in turn results in an error in 'yosys'(version 0.44).

Signed-off-by: Ivan Grigorov grigorovia@ispras.ru

Original design assumes bigger port widths in connections to module 'ramb4_s4_s4'.