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Errors when trying to synthesize gate Verilog (2)

The following tests in test/gate/translator/verilog/gate_verilog_sim_test.cpp (branch gate_verilog_sim) are failing with the following errors:

  • TEST(GateVerilogSimulateComb, SimpleMod) (utests: .../src/gate/synthesizer/synthesizer_div.cpp:37: eda::gate::model::SubnetID eda::gate::synthesizer::synthModU(const eda::gate::model::CellTypeAttr&): Assertion `false && "RemS is unsupported"' failed.)
  • TEST(GateVerilogSimulateComb, SimpleDiv) (utests: .../src/gate/synthesizer/synthesizer_div.cpp:30: eda::gate::model::SubnetID eda::gate::synthesizer::synthDivU(const eda::gate::model::CellTypeAttr&): Assertion `false && "DivU is unsupported"' failed.)
  • TEST(GateVerilogSimulateComb, SimpleMul) (utests: .../src/gate/synthesizer/synthesizer_mul.cpp:30: eda::gate::model::SubnetID eda::gate::synthesizer::synthDivU(const eda::gate::model::CellTypeAttr&): Assertion `false && "MulU is unsupported"' failed.)
Edited by Григоров Иван Александрович