Merge requests · mvg / Utopia EDA · GitLab

Draft: Verilog to GNet2

!97 · created Nov 14, 2023 by Ушаков Александр Николаевич
- Closed
updated Mar 25, 2024
Draft: Image graphviz installation

!209 · created Feb 28, 2024 by Грицун Тимофей Юрьевич
CI/CD & Testing
- Closed
- 3
updated Mar 15, 2024
build fix

!225 · created Mar 07, 2024 by Белин Егор Сергеевич techOpt
TechMapper
- Closed
updated Mar 07, 2024
Links information erasing fix in SubnetBuilder::addSubnet.

!216 · created Mar 03, 2024 by Ягжов Алексей Александрович
- Closed
- 3
updated Mar 07, 2024
Changed root element mapping for cones.

!201 · created Feb 20, 2024 by Ершов Михаил Алексеевич
LogOptimizer
- Closed
updated Mar 07, 2024
Draft: NOT,AND-bi-decomposition -> AND-bi-decomposition.

!179 · created Feb 10, 2024 by Ягжов Алексей Александрович
LogOptimizer
- Closed
- 1
updated Mar 01, 2024
Simulation Estimator test expanding

!212 · created Mar 01, 2024 by Ягжов Алексей Александрович
- Closed
updated Mar 01, 2024
Draft: Decomposition

!136 · created Dec 27, 2023 by Гаряев Даниил Ренатович
Synthesizer
- Closed
- 10
updated Feb 14, 2024
Draft: Resolve "Исправление массива переменной длины (с-style)"

!160 · created Jan 25, 2024 by Знатнов Егор Павлович
- Closed
updated Jan 25, 2024
Draft: LEC refactoring

!154 · created Jan 17, 2024 by Кашинцев Илья Константинович
LogVerifier
- Closed
- 49
updated Jan 23, 2024
Draft: Memory assertion

!112 · created Nov 30, 2023 by Ягжов Алексей Александрович
Synthesizer
- Closed
updated Jan 15, 2024
Draft: Reed muller max arity

!114 · created Dec 02, 2023 by Знатнов Егор Павлович
LogOptimizer
- Closed
- 4
updated Jan 13, 2024
Draft: memory.h assertion

!106 · created Nov 23, 2023 by Ягжов Алексей Александрович
- Closed
updated Jan 04, 2024
Firrtl

!134 · created Dec 27, 2023 by Ушаков Александр Николаевич
- Closed
updated Dec 27, 2023
Draft: Fraig checker

!50 · created Aug 02, 2023 by Кашинцев Илья Константинович
LogVerifier
- Closed
- 34
updated Dec 26, 2023
Draft: model2/list.h assertion

!107 · created Nov 23, 2023 by Ягжов Алексей Александрович
LogOptimizer
- Closed
updated Dec 24, 2023
Draft: Test output fix

!71 · created Sep 28, 2023 by Грицун Тимофей Юрьевич
CI/CD & Testing
- Closed
- 4
updated Dec 21, 2023
Draft: Added max cut finding mode for CutExtractor.

!118 · created Dec 11, 2023 by Ершов Михаил Алексеевич
LogOptimizer
- Closed
updated Dec 20, 2023
FIRRTL to Verilog translator

!103 · created Nov 20, 2023 by Ушаков Александр Николаевич
- Closed
updated Dec 04, 2023
Rtlil

!1 · created Jun 03, 2023 by Ушаков Александр Николаевич
- Closed
updated Dec 04, 2023

Prev
1
2
3
4
Next