Merge requests · mvg / Utopia EDA · GitLab

Added cone extraction function and example of its usage in tests.

!38 · created Jul 26, 2023 by Щербакова Елизавета Александровна
LogOptimizer
- Merged
updated Jan 17, 2024
Ci/cd test

!37 · created Jul 26, 2023 by Грицун Тимофей Юрьевич
- Merged
- 2
updated Jul 27, 2023
Ci/cd building fixed

!36 · created Jul 26, 2023 by Грицун Тимофей Юрьевич
CI/CD & Testing
- Merged
- 2
updated Jan 17, 2024
solveLimited

!35 · created Jul 26, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
- 2
updated Jan 17, 2024
translator from RTLIL to FIR RTL

!34 · created Jul 26, 2023 by Ушаков Александр Николаевич
- Closed
updated Dec 04, 2023
bypasser

!33 · created Jul 26, 2023 by Ушаков Александр Николаевич
- Closed
updated Dec 04, 2023
Counter example in CheckerResult version 2

!32 · created Jul 25, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
- 5
updated Jan 17, 2024
Extra BUF gates removed from miter

!30 · created Jul 24, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
- 1
updated Jan 17, 2024
Yml script for auto building

!28 · created Jul 20, 2023 by Грицун Тимофей Юрьевич
CI/CD & Testing
- Merged
- 3
updated Jan 17, 2024
Find cut parameter

!26 · created Jul 19, 2023 by Щербакова Елизавета Александровна
LogOptimizer
- Merged
- 10
updated Jan 17, 2024
Walker logic is separated. Cone find methods moved to util.

!25 · created Jul 18, 2023 by Щербакова Елизавета Александровна
LogOptimizer
- Merged
updated Jan 17, 2024
Verilog lec tests version №2

!24 · created Jul 17, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
- 32
updated Jan 17, 2024
Hints creation function

!23 · created Jul 16, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
updated Jan 17, 2024
Draft: Bi decomposition

!22 · created Jul 12, 2023 by Ягжов Алексей Александрович
LogOptimizer
- Closed
- 40
updated Sep 25, 2023
Mitering at default checker

!21 · created Jul 11, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
- 12
updated Jan 17, 2024
getter methods for simulator & minor bug fix

!18 · created Jul 07, 2023 by Кашинцев Илья Константинович
Simulator
- Merged
- 5
updated Jan 17, 2024
Unitized Table for Akers algorithm

!17 · created Jul 06, 2023 by Вершков Максим Дмитриевич
LogOptimizer
- Merged
- 81
updated Jan 17, 2024
More bases

!16 · created Jul 03, 2023 by Кашинцев Илья Константинович
LogVerifier
- Merged
updated Jan 17, 2024
GNet->BDD Converter add MAJ3

!15 · created Jul 01, 2023 by Рамалданов Рустамхан Ражудинович
Model
- Merged
updated Jan 17, 2024
Fixed bug: GateVerilogParser doesn't create OUT gates.

!14 · created Jun 30, 2023 by Щербакова Елизавета Александровна
Translator
- Merged
- 26
updated Jan 17, 2024

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