Skip to content
GitLab
Explore
Sign in
mvg
Utopia EDA
Merge requests
Open
22
Merged
212
Closed
34
All
268
Actions
Subscribe to RSS feed
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Created date
Added NPNStatDatabase. Added Serialization for NPNDatabase and NPNStatDatabase.
!287
· created
Apr 28, 2024
by
Рамалданов Рустамхан Ражудинович
0
updated
Apr 28, 2024
shell: add basic shell implementation using TCL
!285
· created
Apr 27, 2024
by
Романов Никита Сергеевич
0
updated
Apr 28, 2024
FraigChecker model2 & performance tests
!283
· created
Apr 26, 2024
by
Кашинцев Илья Константинович
LogOptimizer
6
updated
Apr 27, 2024
Fedora tutorial
!282
· created
Apr 25, 2024
by
Чернявских Илья Игоревич
0
updated
Apr 25, 2024
Draft: Delay estimation
!281
· created
Apr 25, 2024
by
Штренев Владислав
0
updated
Apr 29, 2024
Draft: Model2 opt
!275
· created
Apr 21, 2024
by
Ушаков Александр Николаевич
Translator
0
updated
Apr 29, 2024
Draft: Corasick mapping
!270
· created
Apr 17, 2024
by
Федотова Анна Алексеевна
0
updated
Apr 27, 2024
Draft: YosysConverterModel2 tests
!258
· created
Apr 07, 2024
by
Ушаков Александр Николаевич
0
updated
Apr 13, 2024
Draft: Realized YosysConverterFirrtl tests
!256
· created
Apr 05, 2024
by
Ушаков Александр Николаевич
0
updated
Apr 13, 2024
Draft: Power optimization
!253
· created
Apr 04, 2024
by
Ягжов Алексей Александрович
0
updated
Apr 15, 2024
Draft: Translator Verilog to model2
!235
· created
Mar 25, 2024
by
Ушаков Александр Николаевич
0
updated
Apr 13, 2024
Removed not synth ops & reduce ops.
!228
· created
Mar 13, 2024
by
Григоров Иван Александрович
6
updated
Mar 18, 2024
Draft: TT generating with information about NPN statistics
!226
· created
Mar 10, 2024
by
Ягжов Алексей Александрович
LogOptimizer
5
updated
Mar 15, 2024
Draft: Translator Verilog to Firrtl sys test
!198
· created
Feb 19, 2024
by
Грицун Тимофей Юрьевич
CI/CD & Testing
33
updated
Apr 26, 2024
Draft: Smoke tests suite
!197
· created
Feb 19, 2024
by
Грицун Тимофей Юрьевич
CI/CD & Testing
2
updated
Apr 16, 2024
Draft: Reorganize CMake build scripts
4 of 6 checklist items completed
!196
· created
Feb 18, 2024
by
Artem Kotsynyak
0
updated
Mar 13, 2024
Draft: Resolve "Fix ReedMuller for 2 variables"
!181
· created
Feb 11, 2024
by
Знатнов Егор Павлович
0
updated
Feb 11, 2024
Draft: Resolve "Префиксный сумматор"
!174
· created
Feb 06, 2024
by
Знатнов Егор Павлович
0
updated
Feb 08, 2024
Draft: power_optimization_on_open-ABCD
!168
· created
Feb 01, 2024
by
Курганская Анастасия Сергеевна
200
updated
Feb 01, 2024
Draft: Switching activity estimating in OpenABC-D (GraphMl)
!152
· created
Jan 14, 2024
by
Ягжов Алексей Александрович
1
updated
Apr 09, 2024
Prev
1
2
Next