[verilog] new benchmark for LEC tools (before/after 'rf' Utopia pass)

A new benchmark should be made from *_orig.bench.graphml designs.

It should contain Verilog modules only, grouped in pairs. The first design in pair, called in1.v should be translated directly from original GraphML. The second design, called in2.v, should be created from the first one by applying logopt rf optimization pass in Utopia EDA (logic synthesis open-source framework). All the pairs should be placed in subdirectories are named as original GraphML designs.