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Created date
Verilator 5.028 and Yosys 0.44 treat cases with 'x' differently.
!11
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Verilator 5.028 doesn't support equality operation for tristate logic.
!10
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Yosys 0.44 supports meta comments and Verilator 5.028 doesn't.
!9
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Yosys 0.44 supports meta comments and Verilator 5.028 doesn't.
!8
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Yosys 0.44 supports meta comments and Verilator 5.028 doesn't.
!7
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Verilator 5.028 and Yosys 0.44 treat uncovered cases differently.
!6
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Verilator 5.028 and Yosys 0.44 treat uncovered cases differently.
!5
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Yosys 0.44 doesn't support constructs such as 'time', 'tri0', 'tri1'.
!4
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Original design assumes bigger port widths in connections to module 'ramb4_s4_s4'.
!3
· created
Mar 04, 2025
by
Григоров Иван Александрович
updated
Mar 04, 2025
Draft: Treat 'altsyncram' as a hard block.
!1
· created
Nov 25, 2024
by
Григоров Иван Александрович
1
updated
Nov 26, 2024
