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  • sifive/0/0/8

    106815ae · [FIRRTL] Preserve/Tap all "Named" Nodes or Wires (#2676) · Feb 25, 2022
  • sifive/0/0/7

    65e798e4 · [ExportVerilog] Add $sampled use it in LowerToHW (#2549) · Feb 11, 2022
  • sifive/0/0/6

    bbe0104f · [FIRRTL] Add test of numeric class, NFC · Jan 27, 2022
  • sifive/0/0/5

    bd804370 · [FIRRTL] handle testbench dir annotation in combination with dut annotation (#2382) · Dec 25, 2021
  • sifive/0/0/4

    7b649c5c · [FIRRTL/ExpandWhens] Support aggregate type registers (#2305) · Dec 10, 2021
  • pycde-0.0.3

    c11c3376 · [PyCDE] Remove export_verilog call from System.run_passes. · Nov 10, 2021
  • sifive/0/0/3

    3c087411 · [TableGen] Factor common defs out into common `Types.td` (#2120) · Nov 10, 2021
  • pycde-0.0.2

    c5bda610 · [Python] Add bindings for hw::ParamVerbatimAttr. (#2051) · Oct 28, 2021
  • sifive/0/0/2

    3b9d4f27 · [FIRRTL] Add filename option for seq mem metadata emission (#2005) · Oct 18, 2021
  • pycde-0.0.1

    39bce998 · [Python] Flush error stream in MSFT tests. (#1981) · Oct 12, 2021
  • sifive/0/0/1

    f5441a2d · [HandshakeToFIRRTL] Add support for index_cast, zexti and trunci ops (#1865) · Sep 24, 2021
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