Tags

Tags give the ability to mark specific points in history as being important

sifive/1/4/0

70af75d6 · [FIRRTL][ModuleInliner] Filter HierPaths based on inlining instance. (#3352) · Jun 16, 2022
sifive/1/3/0

c46e46f0 · Fix for clion IDEA settings. (#3291) · Jun 10, 2022
sifive/1/2/0

a79338da · [FIRRTL][IMConstProp] unique constants in module entry (#3264) · Jun 03, 2022
sifive/1/1/0

f0db1d60 · [FIRRTL] Whitespace cleanup, NFC · May 31, 2022
sifive-pre/1/1/1

c18b4ddd · Revert "[FIRRTL] Use tap wires for GCT data taps (#3192)" · May 31, 2022
sifive-pre/1/1/0

23af016b · [CalyxToHW] Add missing Srsh handling · May 28, 2022
sifive/1/0/0

f81f56d2 · [FIRRTL] Fix uses of deprecated APInt functions (#3202) · May 27, 2022
circtorg-0.0.0

b7e1ad37 · [ExportVerilog] Include Build Information in Output Files (#2613) · May 24, 2022
pycde-0.0.5

65553d1e · [PyCDE] Remove AppID and AppIDIndex (#3124) · May 13, 2022
sifive/0/9/0

173962b8 · [FIRRTL] Produce pre-extract seqmem metadata (#3123) · May 13, 2022
sifive/0/8/0

f20d6655 · Fewer Assigns of Constants in ExportVerilog (#3106) · May 11, 2022
sifive/0/7/0

a9bdc67c · [ExportVerilog] Add parentheses around reduction ops if necessary (#3015) · May 10, 2022
sifive/0/6/0

167d0e3a · [FIRRTL] DUT seq mems paths should start from the DUT module. (#3031) · May 03, 2022
sifive/0/5/0

5f6826b7 · [FIRRTL] Grand Central Testharness Fixes (#2864) · Apr 21, 2022
sifive/0/4/0

958a3bbe · [PyCDE][NFC] Cleaning up Values and Types with __new__ (#2914) · Apr 19, 2022
sifive/0/3/0

cb5d0279 · [FIRRTL] Squash Invalids in RemoveInvalid · Apr 12, 2022
sifive/0/2/0

1b604005 · [SV] Remove Verif Statements w/ Non-zero Predicate · Apr 01, 2022
sifive/0/1/0

1041dfda · [MSFT] [PyCDE] Make placement DB global rather than rooted (#2804) · Mar 25, 2022
pycde-0.0.4

c2936b50 · [HW] GlobalRefOp performance enhancement (#2796) · Mar 24, 2022

sifive/0/0/9

3f934d4f · [FIRRTL][LowerToHW] Find the DUT in a prepass (#2784) · Mar 17, 2022

SiFive 0.0.9 (Beta) Release

This covers accumulated bug fixes after the 0.0.8 release from running a
matrix of internal designs through CIRCT.